Paradis channel check: AMD MI450/455 ~600k CoWoS
@ParadisLabs cites MS: AMD MI450/MI455 stay 100% TSMC CoWoS in 2027; mid-point ~600k units; Venice may take ~80k CoWoS-L if OSAT ramps lag.
Opening
Paradis relays a Morgan Stanley-framed AMD / TSMC / OSAT channel check: MI450/MI455 stay 100% on TSMC CoWoS in 2027 at a mid-point ~600k units for both SKUs. @ParadisLabs also says ASE/Amkor CoWoS-adjacent capacity ramps are rumoured slower than expected, which could force TSMC to support CoWoS-L wafers for AMD Venice CPU production and further constrain MI450/MI455 — "~80k CoWoS-L for Venice" per MS in the same post. Primary MS note not opened this pass; treat as secondhand relay. Visible replies mostly agree/amplify the CoWoS gate (no contrary supply figure in the skimmed top replies).
The numbers
MI450/MI455 — mid-point ~600k units next year; 100% TSMC CoWoS in 2027 — MS via Paradis. Venice — ~80k CoWoS-L wafers if TSMC must cover OSAT shortfall — MS via Paradis.
Why it matters
If accurate, AMD's 2027 AI GPU unit path remains packaging-gated at TSMC, and Venice CPU packaging competes for the same scarce CoWoS-L pool — a constraint channel for AMD AI shipments independent of end-demand chatter.
Positioning
HBM supply binds — Adjacent packaging constraint: CoWoS/OSAT tightness can bind accelerator shipments even when HBM is the usual binding narrative.
Connects to
AMD MI355X vs GB300 inference TCO — Prior discussion on whether AMD closes inference TCO; this is a 2027 unit/packaging supply check, not a TCO claim (discussion).
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